FPGA & ASIC Design ContractorWorkingFPGA(2023 ▪ present)

Strategic Solution ArchitectSilicom Denmark(2021 ▪ 2023)

SoC Architect NXP Semiconductors ▪ Munich(2018 ▪ 2021)

Senior FPGA Developer & Team LeadBruel & Kjaer Sound & Vibration(2009 ▪ 2017)

Liaison to Customer R&D (relocation)Nortel ▪ Canada(2001, 6 months)

ASIC Architect & ASIC DesignerVitesse Semiconductors(1998 ▪ 2005) 

HW & FPGA DesignerDSC Communications(1997 ▪ 1998) 

MSc (Electronic Eng.) Technical University of Denmark(1991 ▪ 1997) 

High-Speed Digital Design

• automotive SoC micro-architecture, architectural integration of DSP and AI engines, performance analysis, and analysis and design of functional safety features
• specification, architecture, design, verification, and customer documentation of several deployed communication FPGAs and ASICs: network access for the telecom industry, high-performance, low-latency Ethernet switches, Ethernet switches for the consumer market, and measurement equipment for the automotive industry
• architecture, design, and verification of IP cores with prototyping in FPGA (TCP/IP offload engine)
• STA on several designs
• experienced in laboratory work through validation and debugging of interface timing, signal integrity and power supply quality
• familiar with high-speed PCB design challenges

Liaison & International Work

• positions in multinational companies with a close working relationship between teams and individuals internationally
• technical liaison to sub-contractors, third-party IP providers, partners, and in-house stakeholders (backend design, frontend design, HW design, SW design, verification, validation, production, systems, applications, documentation, customer support)
• close working relationships with customers including 6 months' relocation to customer's premises
• customer support through correspondence as well as face-to-face
• remote and on-site system-setup and problem-solving of customer equipment
• delivering university lectures on standardization and RTL Design
  

Product Management

• product ownership of a 200 Gbit/s accelerator board for 5G edge and Fintech based on Intel Agilex FPGA with Open FPGA Stack
• pre-sale customer activities
• creation of marketing material
  

Problem-Solving & Sparring

• root cause analysis at system and chip level (defects as well as performance)
• pre-silicon performance analysis of sub-systems
• resolving design constraint violations (e.g. performance)
• a valued sparring partner for design, architecture, implementation, and root cause analysis
• identifying viable workarounds for device defects and technical modifications to compensate schedule delays
  

Design Methodology

• established ASIC and FPGA design methodology and automated design flows
• creation of highly sophisticated FPGA test environments for regression verification and laboratory work
• conducted training in tools, methodology, and flows
• creation of Code generators for SW register interfaces – from specification to VHDL, TCL, C++, RTF
• initiatives in product quality improvements

Frontend Design

block design ▪ RTL ▪ high-speed design ▪ low-latency design ▪ reusability ▪ resource sharing ▪ packet processing ▪ stream processing ▪ SW interfaces ▪ high‑speed interfaces ▪ I/O planning ▪ reset ▪ clock domains ▪ synchronization ▪ embedded RAM ▪ external RAM ▪ IP core integration ▪ IP core development ▪ embedded processors ▪ FPGA prototyping ▪ data acquisition ▪ filtering

Testing

test planning ▪ simulation ▪ regression testing ▪ randomization ▪ reproducibility ▪ generic test benches ▪ design for testability ▪ design for debugging ▪ reusability ▪ wireshark ▪ signal tap ▪ signal probe ▪ hands-on lab work ▪ logic analyser ▪ oscilloscope ▪ power supply stability ▪ signal integrity ▪ gate level simulations ▪ test vector generation ▪ design of laboratory test tools ▪ system demos

Backend Design

synthesis ▪ STA ▪ timing closure ▪ floor planning ▪ FPGA routing ▪ scripting ▪ power analysis

System Design

HW & device architecture ▪ requirement specification ▪ design specification ▪ interface specification ▪ SW/HW partitioning ▪ redundancy ▪ testability 

Design Methodology

reusability ▪ structured development ▪ quality assurance ▪ documentation ▪ specification ▪ guidelines ▪ reviews ▪ training ▪ reproducible regression testing ▪ test environment and test bench design ▪ automated documentation ▪ from-spec-to-code generators ▪ requirements management ▪ revision control

Protocols & Standards

Ethernet ▪ PTP-1588 ▪ TCP/IPv4 ▪ PCIe ▪ AXI ▪ CAN Bus ▪ SONET/SDH ▪ proficiency in standards and protocols in general ▪ ISO 26262 ▪ proprietary protocols

Technologies

FPGA ▪ CMOS ASIC ▪ Intel-Altera ▪ AMD-Xilinx ▪ DSP and AI engine IP ▪ NoC

Programming Languages

VHDL ▪ Verilog ▪ TCL ▪ Perl ▪ Bash ▪ Make ▪ JavaScript ▪ Visual Basic