ASIC & FPGA Design Services

Does your project need an FPGA, but you lack in-house FPGA capabilities?

For smaller designs, I can handle the entire development before we bring it up and test it in your lab.

For larger designs, I can head the development effort using your in-house resources and/or contractors.

I can also help to partition the system and deﬁne the requirements together with your teams and other stakeholders.

Does your FPGA or ASIC contain a design block that you don't have the right resources available for?

I can take over implementation of the block in alignment with your development process.

For turnkey FPGA implementations I bring my own toolbox with extensive IP for veriﬁcation, bring-up and debug in laboratory as well as basic RTL blocks.

The IP is licensed to you for use in the FPGA project at no additional cost.

If you do not already have an FPGA development process in place this will provide you with a considerable head start and make the overall development cost for the FPGA very competitive.

Don't have enough hands in your FPGA or ASIC design team?

I can ﬁll in wherever you need it most. In the menu under Services you can ﬁnd a list of areas I can assist in.

20+ Years of Expertise in ASIC and FPGA

You will benefit from my background as a designer, architect, and technical lead in FPGA and ASICs for data ﬂow, packet-switching, and data acquisition. My extensive career includes:

extensive work with Ethernet and experience with AXI, PCIe, DDRx, and numerous other interface technologies.
wide experience in working with standards, extracting relevant information, and ensuring compliance in designs.
considerable experience with board and network synchronization as well as clock and reset design.
experience with the integration of simple and complex third-party IP.
expertise in technical coordination with worldwide, multicultural functional teams inside and outside the organization.

Quality, maintainability, and testability are key for my work, and I consider careful and sufﬁcient communication throughout the project crucial for a successful collaboration.

Let's meet for a chat about how I best can assist you.

Robin Moll Hjort

Services

RTL Design

Well-structured and easy-to-understand RTL design in VHDL or Verilog with carefully selected signal names and sufﬁcient inline commenting to minimize the risk of errors going unnoticed.

IO, clock generation, reset, and clock domain crossings (CDC) are carefully designed and constrained.

Initial synthesis is considered an integral part of any RTL design, as it reveals any structural and performance issues in the RTL.

Verification

Regression veriﬁcation is essential in the process towards a working product. Veriﬁcation targets functional behavior as well as stress and performance.

Veriﬁcation is mainly based on simulation, as debugging is faster in simulation. In FPGA designs however, selected parts of the veriﬁcation can be done in HW to save runtime.

As veriﬁcation can consume a major part of the design time, it is important to align the effort with the project objectives.

Physical Design

Tasks like device conﬁguration, ﬂoor-planning, IO assignment, constraints, synthesis, routing, and timing analysis (STA).

Execution and analysis of the generated reports are scripted to facilitate a simple re-run of the ﬂow.

I am experienced with FPGA devices and tool ﬂow from both Intel (Altera) and AMD (Xilinx).

HW Architecture

Good interface speciﬁcations, re-usability, simplicity, and testability are some of the goals for creating a high-quality product.

I have extensive expertise in device and system architecture as well as micro-architecture.

Laboratory Bring-up & Test

In the bring-up phase, software, hardware, and the FPGA binary come together for the ﬁrst time. Any issues need to be identiﬁed and resolved.

Often, debugging through simple software access to device registers on the board and the FPGA will be sufﬁcient. Sometimes however, an inspection of interfaces and signals with an oscilloscope and logic analyzer may be required.

Establishment of Design Flow

Are you already engaged in FPGA design but wish to improve your process? Do you want your FPGA implementation to be smooth and repeatable?

I can help you establish an appropriate design ﬂow for your needs and ambitions.

Specification

A clear and unambiguous speciﬁcation is the foundation for a successful design and implementation. Drawings and context descriptions improve the quality of work for everyone involved in the process.

Debug & Root Cause Analysis

Issues arise both before and after production releases, so it is essential that you can debug and get to the root cause of issues quickly.

I can help with this with my good system understanding, outstanding analytical skills, curiosity, and persistency. I strive to find the root cause quickly and efficiently through team collaboration and structured analysis.

Review

I can conduct or participate in reviews of speciﬁcations, RTL, PCBs, veriﬁcation and test plans, timing constraints, and documentation.

Technical Leadership

I can assist you in steering your FPGA design through all disciplines and phases.

This includes ensuring that the technical side of the project is aligned with requirements, that the implementation and veriﬁcation is adequate to your needs, and your project ambitions match your resources and deadlines.

Technical Liaison

In projects involving partners and sub-contractors or projects spanning many teams, a huge effort is needed in coordination and technical alignment.

A successful effort requires technical insight, careful communication, strong relations, and an awareness of cultural differences.

Technical Documentation

I can deliver design and usage/user documentation in English or Danish with a quality and comprehension level aligned with needs.

Documentation can be in Microsoft Word or mark-up language.

Examples of documentation are design documentation, architecture speciﬁcation, user manuals, 'how-to' guides, technical notes, application notes etc.